1. Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for a shared line unified cache.
2. Description of the Related Art
Many current system on a chip (SoC) mobile processors do not have a level 3 (L3) cache (also referred to as a last level cache or LLC) because such a cache tends to increase power usage above the desired power threshold. In particular, because L3 caches are often supersets of Level 2 (L2) and Level 1 (L1) caches, they are typically very large and the implementation of a large cache adds power consumption and silicon cost to mobile SoC processors which cannot be tolerated in a low cost, low power product.
However, it would be desirable to utilize the performance provided by a L3 cache, particularly for certain types of applications. For example, when variables are shared by CPU cores, variable-sharing happens when applications are attempt to improve performance through sharing workloads by more than one CPU cores, without a unified cache, shared variables accessed by one CPU core can be evicted by another CPU core who tries to access the same variables. This type of interference is referred to as cache thrashing, and this type of interface is a critical issue for many embedded applications. A unified L3 cache provides common storage that can be accessed by all the CPU cores, so it reduces the frequency of cache thrashing as described above, which, in turn, improves system performance significantly.
Coherency between the L1, L2 and L3 caches may be provided with a cache coherency protocol such as the MESI (Modified, Exclusive, Shared, Invalid) protocol. Using the MESI protocol, every cache line is marked with one of the MESI states (e.g., coded in two additional bits in a cache directory or with the cache line):
Modified (M) State: In the M state, the cache line is present only in the current cache, and has been modified from the value in main memory (i.e., it is “dirty”). The cache is required to write the data back to main memory before permitting any other read of the dirty main memory state. Writing the data back to main memory changes the line to the Exclusive (E) state.
Exclusive (E) State: The cache line is present only in the current cache, but it matches main memory (i.e., it is “clean”). It may be changed to the Shared (S) state in response to a read request by another cache. Alternatively, it may be changed to the Modified (M) if written to.
Shared (S) State: Indicates that this cache line may be stored in other caches of the processor and matches the main memory (i.e., it is “clean”). The line may be discarded by changing to the Invalid (I) state.
Invalid (I) State: Indicates that this cache line is invalid within the current cache (i.e., unused).